Hitherto, attempts have been made to develop double heterojunction bipolar transistors (hereinafter, referred to as “DHBTs”) in order to reduce the offset voltage of transistors.
For example, Japanese Unexamined Patent Application Publication No. 2003-297849 discloses a DHBT that includes a base layer with a two-layer structure including a first base layer composed of GaAsSb that forms a heterojunction with a collector layer composed of InP and a second base layer composed of InGaAs that forms a heterojunction with an emitter layer composed of InP.